1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and is intended for, e.g., a semiconductor device including a CMISFET (Complementary Metal Insulator semiconductor Field Effect Transistor) having a high-dielectric-constant gate insulating film.
2. Related Background Art
In a semiconductor device including an MISFET, a reduction in film thickness of a gate insulating film involved by miniaturization directly increases a tunneling current, and a conventionally utilized silicon oxide film or silicon oxynitride film is confronted with a physical limit in a reduction in film thickness thereof. To achieve both suppression of a leakage current and a reduction in effective film thickness of a gate insulting film, a so-called High-k gate insulating film technology that uses a high-dielectric-constant material such as a hafnium oxide (HfO2) or a hafnium silicon oxynitride (HfSiON) for a gate insulating film has been proposed.
However, when a hafnium oxide (HfO2) or a hafnium silicon oxynitride (HfSiON) is used for the gate insulating film, a problem that a threshold value expected from a work function inherent to an electrode material cannot be obtained is a serious obstacle in practical use of an Hf-based High-k gate insulating film. This phenomenon occurs not only in a case using a polysilicon electrode but also a case using a metal electrode. Giving an explanation while taking an MOS (Metal Oxide Semiconductor) transistor as an example, a threshold voltage of an nMOS is increased when a material having a small work function is used to obtain a low threshold voltage in the nMOS, and (an absolute value of) a threshold voltage of a pMOS is increased when a material having a high work function is used to obtain (an absolute value of) a low threshold voltage in the pMOS.
Thus, there has been proposed a technology that uses a cap layer of, e.g., a lanthanum oxide (La2O3) on an Hf-based High-k insulating film to reduce a threshold voltage Vth of an nMOS or a technology that uses a cap layer of, e.g., Al2O3 on the Hf-based High-k insulating film to reduce a threshold voltage of a pMOS.
However, when simultaneously adopting both the technologies to realize a CMOS is tried, there is a problem that performing realistic integration is difficult. For example, one of the cap layers must be removed from one of the nMOS and the pMOS on the Hf-based High-k gate insulating film, and the other cap layer must be fully deposited and then delaminated from the other of the nMOS and the pMOS.